Multi-level NAND-type flash memory (“NAND memory”) may be organized into multiple cells, with each cell containing multiple bits of data. In such a case, the number of bits per cell may depend on how many distinct voltage levels can be achieved during program operation(s). For example, to support two bits per cell, four voltage levels may be called for in order to distinguish between the four possible combinations of ones and zeros (11, 01, 00, 10). Each bit may have a substantially different read time due to the number of voltage level comparisons that are conducted for the bit in question. For example, in the above example, two comparisons may be involved for the first (e.g., most significant) bit in order to read the bit, whereas only one comparison may be involved for the second (e.g., least significant) bit. Accordingly, reading the second bit may take twice as long as reading the first bit.
This variability may present challenges with regard to the device (e.g., solid state drive/SSD) containing the multi-level NAND memory as well as the system (e.g., server, host, data center) containing the device. For example, the SSD may use a transfer buffer to store data that is being relocated in accordance with a “garbage collection” policy. Designing the transfer buffer to support the longest read times may increase the size of the transfer buffer, which may in turn have a negative impact on performance and cost. Similarly, server resources such as multi-threading read queues within the host processor may be sized to support the longest read times, which may further reduce performance and increase cost.